The present invention relates to a method of controlling data transfer between a high-speed arithmetic memory used by a high-speed arithmetic processor and an input/output device.
In general, a supercomputer has a capability for performing arithmetic processing at very high speed as compared with general purpose computers. The supercomputers allow high-speed solutions of various equations which represent natural phenomena using a large amount of data to achieve various technical studies and developments in scientific and technological fields.
For example, in an aircraft manufacturer, a supercomputer is used to analyze an air whirl formed around each wing. This analysis has been conventionally performed by experiments using a wind tunnel.
In such a supercomputer for performing a large amount of scientific and technological calculations, many problems are involved, and a very large amount of data are required.
A large amount of data, therefore, are stored in a secondary memory device such as a magnetic disk unit, and the data are input/output between the magnetic disk and a high-speed arithmetic memory, as needed, thus performing calculations.
More specifically, the larger a ratio of a transfer period of time between the secondary emory device and the high-speed arithmetic memory is, as compared with a transfer period of time executed between an arithmetic processor and the high-speed arithmetic memory at high speed, the larger an adverse effect to an execution performance of an entire program becomes.
Conventionally, a supercomputer of this type includes a system control unit, an input/output processor connected to the system control unit, a control processor, a control memory mainly used for these processors, a high-speed arithmetic processor, and a high-speed arithmetic memory mainly used for the high-speed arithmetic processor.
In a data transfer operation between the secondary memory device and the high-speed arithmetic memory in a conventional data processing apparatus of this type, the control processor serves as a main unit, and the data contents transferred from the input/output processor to the control memory are transferred to the high-speed arithmetic memory, or the contents are directly transferred from the input/output processor to the high-speed arithmetic memory.
In this method, however, a rate of transfer to the high-speed arithmetic memory is undesirably limited by a rate of transfer from the control processor or the input/output processor to the control memory.
In general, the rate of transfer from the control processor or the input/output processor to the control memory is considerably lower than that between the high-speed arithmetic processor and the high-speed arithmetic memory. As a result, a ratio of an input/output period of time between the secondary memory device and the high-speed arithmetic memory is undesirably larger than a transfer period of time between the high-speed arithmetic processor and the high-speed arithmetic memory.
More specifically, in the above-mentioned conventional data processing apparatus, a transfer period of time between the secondary memory device and the high-speed arithmetic memory is undesirably longer than that between the high-speed arithmetic processor and the high-speed arithmetic memory, and an execution period of time of the entire program may also be increased, thus degrading performance of the apparatus.